The present invention relates to pulse generating circuitry, and in particular, to a pulse generating circuit for generating a pulse signal with a pulse width that is approximately greater than or equal to half the period of an input clock signal.
Pulse generator circuits are commonly used in digital logic applications for generating electrical pulse signals that are triggered as a result of an input clock signal. Often, the pulse generator circuits are used to generate an output pulse signal having a pulse width that is less than half the length of the input clock signal.
FIG. 1 is an example schematic diagram of a pulse generator circuit 10. NCLK is an input clock signal 12 that is input to a two-input NOR gate 14. The input clock signal NCLK also passes through three series-connected inverters 16, 18, and 20 and into the two-input NOR gate. Each inverter delays the input clock signal NCLK by one gate, thus, the three series-connected inverters delay the input clock signal NCLK by a total of three gate before the three-times inverted input clock signal NCLK is input to the two-input NOR gate. Thus, the output pulse signal D 22 is generated by NORing the input clock signal NCLK and the three-times inverted input clock signal NCLK.
FIG. 2 is a timing diagram showing the operation of the pulse generator circuit 10 of FIG. 1. As shown in FIG. 2, NCLK 12 has a period 23 of ten gate and a 50:50 duty cycle. D 22 is an output pulse signal whose leading edge 24 is triggered by the falling edge 26 of NCLK. Also, the pulse width 28 of output pulse signal D is determined by the number of inverter delays which in this case is three gate.
One problem associated with the pulse generator circuit 10 of FIG. 1 is that the number of inverters cannot be increased so that the pulse width 28 of the output signal D 22 is approximately half the period of the input clock signal NCLK 12. For example, if the pulse generator circuit of FIG. 1 includes more than five series-connected inverters, the width 28 of the output pulse signal D exceeds five gate and a rising edge 30 of the input clock signal NCLK occurs faster than an expected rising edge of a signal DLY 32 output from the third inverter 20. Therefore, the rising edge of the input clock signal NCLK limits the width of the output pulse signal D to less than half the period of the input clock signal NCLK. Thus, there is a need for a pulse generator circuit that can generate an output pulse signal having a pulse width approximately equal to, or greater than, half the period of the input clock signal.
An exemplary system that embodies the invention is a pulse generator circuit including a first logic element, a first delay element, a second logic element, and a second delay element. The first logic element has one input for receiving an input clock signal. The first delay element is for delaying the input clock signal by a first delay time. The first delay element has one end for receiving the input clock signal and another end coupled to another input of the first logic element. The second logic element has one input for receiving a signal output from the first logic element where the one input is coupled to an output of the first logic element. The second delay element is for delaying the signal output from the first logic element by a second delay time. The second delay element is coupled at one end to the output of the first logic element and coupled at another end to another input of the second logic element.
Another pulse generator circuit includes a first logic means, a first delay means, a second logic means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.
A method for generating a pulse signal includes receiving an input clock signal at an input of a first logic element, delaying the input clock signal by a first delay time, receiving the input clock signal delayed by a first delay time at another input of the first logic element, receiving an output signal from the first logic element at an input of a second logic element, delaying the output signal from the first logic element by a second delay time, and receiving the output signal from the first logic element delayed by the second delay time at another input to the second logic element.
Other aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, which shows and describes exemplary embodiments of the invention, simply by way of illustration of the best mode contemplated for carrying out the invention. The invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.